The present invention relates to a page buffer of a flash memory device and a programming method using the same, in which two pages can be programmed through one programming operation.
A flash memory is a kind of a non-volatile memory in which data can be stored even when the power is turned off. The flash memory can be electrically programmed and erased and does not need a refresh function of rewriting data at regular intervals. The term “program” refers to the operation of programming data into the memory cells and the term “erase” refers to the operation of erasing data from the memory cells.
The flash memory device can be mainly classified into a NOR flash memory device and a NAND flash memory device depending on the structure of the cell and operation conditions. In a NOR flash memory device, the source of each memory cell transistor is connected to the ground terminal (VSS) and programmed and erased for possible predetermined addresses. Accordingly, the NOR flash memory has been mainly used for application fields requiring the high-speed operation.
On the other hand, in a NAND flash memory device, a plurality of memory cells are connected in series to form one string. One string is connected to the source and drain. The NAND flash memory has been mainly used for high integration data retention related fields.
The NAND flash memory device employs a page buffer in order to store a large capacity of information or read stored information within a short period of time. The page buffer supplies a large capacity of data, which are received from an input/output pad, to memory cells, or stores data of memory cells and outputs the stored data.
The page buffer generally includes a single register in order to temporarily store data. Recently, a dual register has been used in the NAND flash memory device in order to improve the program speed when programming a large capacity of data.
FIG. 1 is a block diagram illustrating the stack structure of page buffers of a conventional NAND flash memory device.
Referring to FIG. 1, a pair of bit lines (i.e., two bit lines) are commonly connected to one page buffer. Accordingly, one page is programmed through one programming operation.
FIG. 2A illustrates a program time consumed during a normal programming operation.
In FIG. 2A, 100 μs denotes a time taken to input data to the page buffer. 300 μs denotes a time taken to program the data input to the page buffer into a corresponding memory cell. The page buffer includes one latch circuit. Accordingly, a total of 1600 μs program time is taken to program four pages through the normal programming operation.
In the normal programming method, both the data input time and the data program time are taken to program one page. Accordingly, a great amount of program time is taken compared with the cache program.
FIG. 2B illustrates a program time taken during the existing cache programming operation. In FIG. 2B, the page buffer includes two latch circuits (i.e., a main latch circuit and a cache latch circuit).
In FIG. 2B, 100 μs that is shown in FIG. 2B denotes a time which is taken from when data are input to the cache latch of the page buffer to when the data input to the cache latch are transferred to the main latch; 300 μs denotes a time which is taken to program the data input to the main latch of the page buffer into a corresponding memory cell. At this time, an operation is performed for inputting data to the cache latch of the page buffer, and then for transferring the data, which have been input to the cache latch, to the main latch.
Therefore, only an operating time taken to input data is required. Thereafter, in the case where four pages are programmed using the cache program method with the data input time being buried in the program time, a total of 1300 μs program time is consumed.
As described above, the cache programming method is disadvantageous in that an additional cache latch is required and the number of cells that can be programmed once does not exceed one page.